[python] 手把手教你使用RT-Thread制作GD32系列BSP

import rtconfig #导包
from building import *
# get current directory
cwd = GetCurrentDir() #获取当然路径
# The set of source files associated with this SConscript file.
src = Split('''
CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c
GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c
GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c
GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c
GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c
GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c
''')#将括号中的字符串分割后成列表(list)，以便包含到工程中
if GetDepend(['RT_USING_SERIAL']):#如果打开了RT_USING_SERIAL的宏，则会包含以下源文件
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c']
if GetDepend(['RT_USING_I2C']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c']
if GetDepend(['RT_USING_SPI']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c']
if GetDepend(['RT_USING_CAN']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c']
if GetDepend(['BSP_USING_ETH']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c']
if GetDepend(['RT_USING_ADC']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c']
if GetDepend(['RT_USING_DAC']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c']
if GetDepend(['RT_USING_RTC']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c']
if GetDepend(['RT_USING_WDT']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c']
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c']
if GetDepend(['RT_USING_SDIO']):
  src += ['GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c']
#头文件路径
path = [
  cwd + '/CMSIS/GD/GD32F4xx/Include',
  cwd + '/CMSIS',
  cwd + '/GD32F4xx_standard_peripheral/Include',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER']
#定义一个组，组名为'Libraries', depend为空表示依赖任何一个其他宏，另外当前的头文件路径添加到工程中
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

config SOC_FAMILY_GD32
  bool
config SOC_SERIES_GD32F4
  bool
  select ARCH_ARM_CORTEX_M4
  select SOC_FAMILY_GD32

Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
""")
# add pin drivers.
if GetDepend('RT_USING_PIN'):
  src += ['drv_gpio.c']
# add usart drivers.
if GetDepend(['RT_USING_SERIAL']):
  src += ['drv_usart.c']
# add adc drivers.
if GetDepend('RT_USING_ADC'):
  src += ['drv_adc.c']
# add i2c drivers.
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
  if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3'):
    src += ['drv_soft_i2c.c']
# add spi drivers.
if GetDepend('RT_USING_SPI'):
  src += ['drv_spi.c']   
# add spi flash drivers.
if GetDepend('RT_USING_SFUD'):
  src += ['drv_spi_flash.c', 'drv_spi.c']   
# add hwtimer drivers.
if GetDepend('RT_USING_HWTIMER'):
  src += ['drv_hwtimer.c']
# add rtc drivers.
if GetDepend('RT_USING_RTC'):
  src += ['drv_rtc.c']
# add iwdt drivers.
if GetDepend('RT_USING_WDT'):
  src += ['drv_iwdt.c']
path =  [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

if BSP_USING_USBD
  config BSP_USBD_TYPE_FS
    bool
    # "USB Full Speed (FS) Core"
  config BSP_USBD_TYPE_HS
    bool
    # "USB High Speed (HS) Core"
  config BSP_USBD_SPEED_HS
    bool 
    # "USB High Speed (HS) Mode"
  config BSP_USBD_SPEED_HSINFS
    bool 
    # "USB High Speed (HS) Core in FS mode"
  config BSP_USBD_PHY_EMBEDDED
    bool 
    # "Using Embedded phy interface"
  config BSP_USBD_PHY_UTMI
    bool 
    # "UTMI: USB 2.0 Transceiver Macrocell Interace"
  config BSP_USBD_PHY_ULPI
    bool 
    # "ULPI: UTMI+ Low Pin Interface"
endif

import os
import sys
import shutil
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
def bsp_update_board_kconfig(dist_dir):
  # change board/kconfig path
  if not os.path.isfile(os.path.join(dist_dir, 'board/Kconfig')):
    return
  with open(os.path.join(dist_dir, 'board/Kconfig'), 'r') as f:
    data = f.readlines()
  with open(os.path.join(dist_dir, 'board/Kconfig'), 'w') as f:
    for line in data:
      if line.find('../libraries/gd32_drivers/Kconfig') != -1:
        position = line.find('../libraries/gd32_drivers/Kconfig')
        line = line[0:position] + 'libraries/gd32_drivers/Kconfig"\n'
      f.write(line)
# BSP dist function
def dist_do_building(BSP_ROOT, dist_dir):
  from mkdist import bsp_copy_files
  import rtconfig
  print("=> copy gd32 bsp library")
  library_dir = os.path.join(dist_dir, 'libraries')
  library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
  bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE),
           os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE))
  print("=> copy bsp drivers")
  bsp_copy_files(os.path.join(library_path, 'gd32_drivers'), os.path.join(library_dir, 'gd32_drivers'))
  shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
  bsp_update_board_kconfig(dist_dir)

mainmenu "RT-Thread Configuration"
config BSP_DIR
  string
  option env="BSP_ROOT"
  default "."
config RTT_DIR
  string
  option env="RTT_ROOT"
  default "../../.."
config PKGS_DIR
  string
  option env="PKGS_ROOT"
  default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"

# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
  path = os.path.join(cwd, d)
  if os.path.isfile(os.path.join(path, 'SConscript')):
    objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
  RTT_ROOT = os.getenv('RTT_ROOT')
else:
  RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
  from building import *
except:
  print('Cannot found RT-Thread root directory, please check RTT_ROOT')
  print(RTT_ROOT)
  exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
  AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
  CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
  AR = rtconfig.AR, ARFLAGS = '-rc',
  CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
  LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
  env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
  env.Replace(ARFLAGS = [''])
  env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
  libraries_path_prefix = SDK_ROOT + '/libraries'
else:
  libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
gd32_library = 'GD32F4xx_Firmware_Library'
rtconfig.BSP_LIBRARY_TYPE = gd32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

#ifndef CCONFIG_H__
#define CCONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* compiler configure file for RT-Thread in GCC*/
#define HAVE_NEWLIB_H 1
#define LIBC_VERSION "newlib 2.4.0"
#define HAVE_SYS_SIGNAL_H 1
#define HAVE_SYS_SELECT_H 1
#define HAVE_PTHREAD_H 1
#define HAVE_FDSET 1
#define HAVE_SIGACTION 1
#define GCC_VERSION_STR "5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]"
#define STDC "2011"
#endif

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__   = 0x082FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_heap__   = 0x2000;
/**** End of ICF editor section. ###ICF###*/
export symbol __ICFEDIT_region_RAM_end__;
define symbol __region_RAM1_start__ = 0x10000000;
define symbol __region_RAM1_end__   = 0x1000FFFF;
define memory mem with size = 4G;
define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
define region RAM1_region  = mem:[from __region_RAM1_start__   to __region_RAM1_end__];
define block CSTACK  with alignment = 8, size = __ICFEDIT_size_cstack__   { };
define block HEAP    with alignment = 8, size = __ICFEDIT_size_heap__   { };
initialize by copy { readwrite };
do not initialize  { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region   { readonly };
place in RAM_region   { readwrite,
            block CSTACK, block HEAP };            
place in RAM1_region  { section .sram };

/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
  CODE (rx) : ORIGIN = 0x08000000, LENGTH = 3072k /* 3072KB flash */
  DATA (rw) : ORIGIN = 0x20000000, LENGTH =  192k /* 192KB sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
  .text :
  {
    . = ALIGN(4);
    _stext = .;
    KEEP(*(.isr_vector))      /* Startup code */
    . = ALIGN(4);
    *(.text)            /* remaining code */
    *(.text.*)            /* remaining code */
    *(.rodata)            /* read-only data (constants) */
    *(.rodata*)
    *(.glue_7)
    *(.glue_7t)
    *(.gnu.linkonce.t*)
    /* section information for finsh shell */
    . = ALIGN(4);
    __fsymtab_start = .;
    KEEP(*(FSymTab))
    __fsymtab_end = .;
    . = ALIGN(4);
    __vsymtab_start = .;
    KEEP(*(VSymTab))
    __vsymtab_end = .;
    . = ALIGN(4);
    /* section information for initial. */
    . = ALIGN(4);
    __rt_init_start = .;
    KEEP(*(SORT(.rti_fn*)))
    __rt_init_end = .;
    . = ALIGN(4);
    . = ALIGN(4);
    _etext = .;
  } > CODE = 0
  /* .ARM.exidx is sorted, so has to go in its own output section.  */
  __exidx_start = .;
  .ARM.exidx :
  {
    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
    /* This is used by the startup in order to initialize the .data secion */
    _sidata = .;
  } > CODE
  __exidx_end = .;
  /* .data section which is used for initialized data */
  .data : AT (_sidata)
  {
    . = ALIGN(4);
    /* This is used by the startup in order to initialize the .data secion */
    _sdata = . ;
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d*)
    . = ALIGN(4);
    /* This is used by the startup in order to initialize the .data secion */
    _edata = . ;
  } >DATA
  .stack : 
  {
    . = . + _system_stack_size;
    . = ALIGN(4);
    _estack = .;
  } >DATA
  __bss_start = .;
  .bss :
  {
    . = ALIGN(4);
    /* This is used by the startup in order to initialize the .bss secion */
    _sbss = .;
    *(.bss)
    *(.bss.*)
    *(COMMON)
    . = ALIGN(4);
    /* This is used by the startup in order to initialize the .bss secion */
    _ebss = . ;
    *(.bss.init)
  } > DATA
  __bss_end = .;
  _end = .;
  /* Stabs debugging sections.  */
  .stab      0 : { *(.stab) }
  .stabstr     0 : { *(.stabstr) }
  .stab.excl   0 : { *(.stab.excl) }
  .stab.exclstr  0 : { *(.stab.exclstr) }
  .stab.index  0 : { *(.stab.index) }
  .stab.indexstr 0 : { *(.stab.indexstr) }
  .comment     0 : { *(.comment) }
  /* DWARF debug sections.
   * Symbols in the DWARF debugging sections are relative to the beginning
   * of the section so we begin them at 0.  */
  /* DWARF 1 */
  .debug      0 : { *(.debug) }
  .line       0 : { *(.line) }
  /* GNU DWARF 1 extensions */
  .debug_srcinfo  0 : { *(.debug_srcinfo) }
  .debug_sfnames  0 : { *(.debug_sfnames) }
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  .debug_aranges  0 : { *(.debug_aranges) }
  .debug_pubnames 0 : { *(.debug_pubnames) }
  /* DWARF 2 */
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  .debug_abbrev   0 : { *(.debug_abbrev) }
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  .debug_weaknames 0 : { *(.debug_weaknames) }
  .debug_funcnames 0 : { *(.debug_funcnames) }
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  .debug_varnames  0 : { *(.debug_varnames) }
}

; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00300000  {  ; load region size_region
  ER_IROM1 0x08000000 0x00300000  {  ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x20000000 0x00030000  {  ; RW data
   .ANY (+RW +ZI)
  }
}

#ifndef __BOARD_H__
#define __BOARD_H__
#include "gd32f4xx.h"
#include "drv_usart.h"
#include "drv_gpio.h"
#include "gd32f4xx_exti.h"
#define EXT_SDRAM_BEGIN  (0xC0000000U) /* the begining address of external SDRAM */
#define EXT_SDRAM_END    (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-64>
//  <i>Default: 64
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__;
#define GD32_SRAM_END      &__ICFEDIT_region_RAM_end__
#else
#define GD32_SRAM_SIZE     192
#define GD32_SRAM_END      (0x20000000 + GD32_SRAM_SIZE * 1024)
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN  (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN  (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN  (&__bss_end)
#endif
#define HEAP_END      GD32_SRAM_END
#endif

#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
/**
  * @brief  This function is executed in case of error occurrence.
  * @param  None
  * @retval None
  */
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler */
  /* User can add his own implementation to report the HAL error return state */
  while (1)
  {
  }
  /* USER CODE END Error_Handler */
}
/** System Clock Configuration
*/
void SystemClock_Config(void)
{
  SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  NVIC_SetPriority(SysTick_IRQn, 0);
}
/**
 * This is the timer interrupt service routine.
 *
 */
void SysTick_Handler(void)
{
  /* enter interrupt */
  rt_interrupt_enter();
  rt_tick_increase();
  /* leave interrupt */
  rt_interrupt_leave();
}
/**
 * This function will initial GD32 board.
 */
void rt_hw_board_init()
{
  /* NVIC Configuration */
#define NVIC_VTOR_MASK        0x3FFFFF80
#ifdef  VECT_TAB_RAM
  /* Set the Vector Table base location at 0x10000000 */
  SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
#else  /* VECT_TAB_FLASH  */
  /* Set the Vector Table base location at 0x08000000 */
  SCB->VTOR  = (0x08000000 & NVIC_VTOR_MASK);
#endif
  SystemClock_Config();
#ifdef RT_USING_COMPONENTS_INIT
  rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
  rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef BSP_USING_SDRAM
  rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
#else
  rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}

menu "Hardware Drivers Config"
config SOC_GD32407V
  bool 
  select SOC_SERIES_GD32F4
  select RT_USING_COMPONENTS_INIT
  select RT_USING_USER_MAIN
  default y
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
  config BSP_USING_GPIO
    bool "Enable GPIO"
    select RT_USING_PIN
    default y
  menuconfig BSP_USING_UART
    bool "Enable UART"
    default y
    select RT_USING_SERIAL
    if BSP_USING_UART
      config BSP_USING_UART1
        bool "Enable UART1"
        default y
      config BSP_UART1_RX_USING_DMA
        bool "Enable UART1 RX DMA"
        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
        default n
    endif
  menuconfig BSP_USING_SPI
    bool "Enable SPI BUS"
    default n
    select RT_USING_SPI
    if BSP_USING_SPI
      config BSP_USING_SPI1
        bool "Enable SPI1 BUS"
        default n
      config BSP_SPI1_TX_USING_DMA
        bool "Enable SPI1 TX DMA"
        depends on BSP_USING_SPI1
        default n
      config BSP_SPI1_RX_USING_DMA
        bool "Enable SPI1 RX DMA"
        depends on BSP_USING_SPI1
        select BSP_SPI1_TX_USING_DMA
        default n
    endif
  menuconfig BSP_USING_I2C1
    bool "Enable I2C1 BUS (software simulation)"
    default n
    select RT_USING_I2C
    select RT_USING_I2C_BITOPS
    select RT_USING_PIN
    if BSP_USING_I2C1
      config BSP_I2C1_SCL_PIN
        int "i2c1 scl pin number"
        range 1 216
        default 24
      config BSP_I2C1_SDA_PIN
        int "I2C1 sda pin number"
        range 1 216
        default 25
    endif
  source "../libraries/gd32_drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
''')
path =  [cwd]
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
  src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S']
elif rtconfig.CROSS_TOOL == 'keil':
  src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
  src += [startup_path_prefix + '/GD32F4xx_HAL/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s']
CPPDEFINES = ['GD32F407']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

#include <stdio.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
/* defined the LED2 pin: PC6 */
#define LED2_PIN GET_PIN(C, 6)
int main(void)
{
  int count = 1;
  /* set LED2 pin mode to output */
  rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
  while (count++)
  {
    rt_pin_write(LED2_PIN, PIN_HIGH);
    rt_thread_mdelay(500);
    rt_pin_write(LED2_PIN, PIN_LOW);
    rt_thread_mdelay(500);
  }
  return RT_EOK;
}